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VN5010AK-E
High side driver with analog current sense for automotive applications
Features
Max supply voltage Operating voltage range Max On-State resistance Current limitation (typ) Off state supply current (typ)
VCC
41V
VCC 4.5 to 36V RON ILIMH IS 10 m 65A 2 A
PowerSSO-24TM
- Electrostatic discharge protection
Application
Main features - Inrush current active management by power limitation - Very low stand-by current - 3.0v CMOS compatible input - Optimized electromagnetic emission - Very low electromagnetic susceptibility - In compliance with the 2002/95/EC European directive Diagnostic functions - Proportional load current sense - High current sense precision for wide range currents - Current sense disable - Thermal shutdown indication - Very low current sense leakage Protections - Undervoltage shut-down - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Thermal shut down - Reverse battery protection (see Application schematic ) Device summary
Package Tube PowerSSO-24
TM
All types of resistive, inductive and capacitive loads
Description
The VN5010AK-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shutdown intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.
Table 1.
Order codes Tape and Reel VN5010AKTR-E
VN5010AK-E
February 2008
Rev 4
1/31
www.st.com 31
Contents
VN5010AK-E
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1 3.1.2 Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 21 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 22
3.2 3.3 3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Maximum demagnetization energy (VCC=13.5V) . . . . . . . . . . . . . . . . . . . 23
4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-24TM thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 5.2 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
VN5010AK-E
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC=13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current sense (8V3/31
List of figures
VN5010AK-E
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay response time between rising edge of ouput current and rising edge of Current Sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IOUT/ISENSE vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Off State output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 On state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Maximum turn Off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-24TM PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 24 PowerSSO-24TM thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25 Thermal fitting model of a double channel HSD in PowerSSO-24TM . . . . . . . . . . . . . . . . . 25 PowerSSO-24TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PowerSSO-24TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-24TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4/31
VN5010AK-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
VCC
VCC CLAMP
UNDERVOLTAGE PwCLAMP
DRIVER
OUTPUT ILIM VDSLIM
GND LOGIC INPUT PwrLIM
OVERTEMP. IOUT CS_DIS K CURRENT SENSE
Table 2.
Name VCC OUTPUT GND INPUT
Pin function
Function Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state. Analog current sense pin, delivers a current proportional to the load current. Active high CMOS compatible pin, to disable the current sense pin.
CURRENT SENSE CS_DIS
5/31
Block diagram and pin description Figure 2. Connection diagram (top view)
VN5010AK-E
VCC GND NC NC INPUT NC CURRENT SENSE NC CS_DIS NC NC VCC
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
NC NC NC OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT NC NC NC TAB = Vcc
Table 3.
Suggested connections for unused and N.C. pins
Current Sense N.R.(1) Through 1k resistor N.C. X X Output X N.R. Input X Through 10k resistor CS_DIS X Through 10k resistor
Connection / Pin Floating To Ground
1. Not recommended.
6/31
VN5010AK-E
Electrical specifications
2
Electrical specifications
Figure 3. Current and voltage conventions
IS VCC VCC IOUT CS_DIS OUTPUT VOUT IIN INPUT CURRENT SENSE VIN VSENSE GND IGND ISENSE
ICSD VCSD
Note:
VFn = VOUT - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the "Absolute maximum ratings" tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol VCC -VCC - IGND IOUT - IOUT IIN ICSD DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current DC Current Sense disable input current
Absolute maximum ratings
Parameter Value 41 0.3 200 Internally limited 30 -1 to 10 -1 to 10 200 Unit V V mA A A mA mA mA
-ICSENSE DC reverse CS pin current
7/31
Electrical specifications Table 4.
Symbol
VN5010AK-E
Absolute maximum ratings (continued)
Parameter Value VCC-41 +VCC 609 4000 2000 750 -40 to 150 -55 to 150 Unit V V mJ V V C C
VCSENSE Current Sense maximum voltage EMAX VESD VESD Tj Tstg Maximum switching energy (single pulse) (L=1.25mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.) ) Electrostatic discharge (Human Body Model: R=1.5K; C=100pF) - INPUT Charge device model (CDM-AEC-Q100-011) Junction operating temperature Storage temperature
Table 5.
Symbol
Thermal data
Parameter Max value 0.3 See Figure 29. Unit C/W C/W
Rthj-case Thermal resistance junction-case (MAX) Rthj-amb Thermal resistance junction-ambient (MAX)
8/31
VN5010AK-E
Electrical specifications
2.2
Electrical characteristics
Values specified in this section are for 8V< VCC< 36V; -40C< Tj< 150C, unless otherwise stated (for each channel). Table 6.
Symbol VCC VUSD VUSDhyst RON Vclamp IS IL(off) VF
Power section
Parameter Operating supply voltage Undervoltage shutdown Undervoltage shutdown hysteresis On state resistance Clamp voltage Supply current Off state output current Output - VCC diode voltage IOUT= 6A; Tj= 25C IOUT= 6A; Tj= 150C ICC= 20 mA Off State; VCC= 13V; Tj= 25C; VIN=VOUT=VSENSE=VCSD=0V VIN=VOUT=0V; VCC= 13V; Tj= 25C VIN=VOUT=0V; VCC= 13V; Tj= 125C -IOUT= 10A; Tj= 150C 0 0 41 46 2(1) 0.01 Test conditions Min. 4.5 Typ. Max. Unit 13 3.5 0.5 10 20 52 5(1) 3 5 0.7 36 4.5 V V V m m V A A V
1. PowerMOS leakage included.
.
Table 7.
Symbol td(on) td(off) (dVOUT/dt)on (dVOUT/dt)off WON WOFF
Switching (VCC=13V)
Parameter Turn-On delay time Turn-Off delay time Turn-On voltage slope Turn-Off voltage slope Switching energy losses during twon Switching energy losses during twoff Test conditions RL= 2.6 (see Figure 8.) RL= 2.6 (see Figure 8.) RL= 2.6 RL= 2.6 RL= 2.6 (see Figure 8.) RL= 2.6 (see Figure 8.) Min. Typ. 35 65 See Figure 20 See Figure 22 1.5 0.8 Max. Unit s s V/ s V/ s mJ mJ
9/31
Electrical specifications Table 8.
Symbol VIL IIL VIH IIH VI(hyst) VICL VCSDL ICSDL VCSDH ICSDH
VN5010AK-E
Logic input
Parameter Input low level voltage Low level input current Input high level voltage High level input current Input hysteresis voltage Input clamp voltage CS_DIS low level voltage Low level CS_DIS current CS_DIS high level voltage High level CS_DIS current VCSD= 2.1V 0.25 ICSD= 1mA ICSD= -1mA 5.5 -0.7 7 VCSD= 0.9V 1 2.1 10 IIN= 1mA IIN= -1mA VIN= 2.1V 0.25 5.5 -0.7 0.9 7 VIN= 0.9V 1 2.1 10 Test conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V
VCSD(hyst) CS_DIS hysteresis voltage VCSCL CS_DIS clamp voltage
Table 9.
Symbol IlimH IlimL TTSD TR TRS THYST
Protections and diagnostics(1)
Parameter Short circuit current Short circuit current during thermal cycling Shutdown temperature Reset temperature Thermal reset of STATUS Thermal hysteresis (TTSD-TR) VCC -41 Test conditions VCC= 13V 5V24 175 TRS+5
VDEMAG Turn-Off output voltage clamp IOUT=2A; VIN=0; L=6mH VON Output voltage drop limitation IOUT=0.5A (see Figure 9.); Tj= -40C...+150C
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
10/31
VN5010AK-E Table 10.
Symbol
Electrical specifications Current sense (8VParameter Test conditions IOUT= 0.25A; VSENSE=0.5V;VCSD=0V; Tj= -40C...150C IOUT= 6A; VSENSE=0.5V; VCSD=0V; Tj= -40C...150C IOUT= 6A; VSENSE=0.5V; VCSD=0V; Tj= 25C...150C IOUT= 6A; VSENSE= 0.5V; VCSD= 0V; TJ= -40 C to 150 C IOUT= 10A; VSENSE=4V; VCSD=0V; Tj=-40C...150C IOUT= 10A; VSENSE=4V; VCSD=0V; Tj=25C...150C IOUT= 10A; VSENSE= 4V; VCSD=0V; TJ= -40 C to 150 C IOUT= 25A; VSENSE=4V; VCSD=0V; Tj= -40C...150C IOUT= 25A; VSENSE=4V; VCSD=0V; Tj= 25C...150C IOUT= 25A; VSENSE= 4V; VCSD=0V; TJ= -40 C to 150 C IOUT= 0A; VSENSE=0V; VCSD= 5V; VIN=0V; Tj= -40C...150C VCSD= 0V; VIN=5V; Tj= -40C...150C IOUT= 2A; VSENSE=0V; VCSD=5V; VIN=5V; Tj= -40C...150C IOL Openload On state current detection threshold Max analog sense output voltage Analog sense output voltage in overtemperature condition Analog sense output current in overtemperature condition VIN = 5V, ISENSE= 5 A Min. Typ. Max. Unit
K0
IOUT/ISENSE
2770 5490 8220
K1
IOUT/ISENSE
3610 4580 5630 3930 4580 5230 -8 +8 %
dK1/K1(1)
Current sense ratio drift
K2
IOUT/ISENSE
4000 4570 5220 4180 4570 4960 -5 +5 %
dK2/K2(1)
Current sense ratio drift
K3
IOUT/ISENSE
4480 4660 4980 4500 4660 4820 -3 +3 %
dK3/K3(1)
Current sense ratio drift
ISENSE0
Analog sense leakage current
0 0
1 2
A A
0 10
1 45
A mA
VSENSE
IOUT=15A; VCSD=0V;
5
V
VSENSEH
VCC= 13V; RSENSE= 3.9K
9
V
ISENSEH
VCC= 13V; VSENSE= 5V
8
mA
11/31
Electrical specifications Table 10.
Symbol
VN5010AK-E
Current sense (8VParameter Test conditions VSENSE<4V, 1.5ADelay response time tDSENSE1H from falling edge of CS_DIS pin Delay response time tDSENSE1L from rising edge of CS_DIS pin Delay response time tDSENSE2H from rising edge of INPUT pin Delay response time between rising edge tDSENSE2H of output current and rising edge of current sense Delay response time tDSENSE2L from falling edge of INPUT pin
50
100
s
5
20
s
270
500
s
310
s
250
s
1. Parameter guaranteed by design; it is not tested.
Figure 4.
Current sense delay characteristics
INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L
12/31
VN5010AK-E Figure 5.
Electrical specifications Delay response time between rising edge of ouput current and rising edge of Current Sense (CS enabled)
VIN
tDSENSE2H
t IOUT
IOUTMAX
90% IOUTMAX
t ISENSE
ISENSEMAX
90% ISENSEMAX
t
13/31
Electrical specifications Figure 6. IOUT/ISENSE vs. IOUT (see Table 10. for details)
VN5010AK-E
IOUT/ISENSE
6000
max Tj = -40C to 150C
5500
5000
max Tj= 25C to 150C typical value
4500
min Tj= 25C to 150C
4000
min Tj= -40C to 150C
3500
3000 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
IOUT (A)
Figure 7.
Maximum current sense ratio drift vs load current dk/k(%)
15 10 5 0 -5 -10 -15 5 10 15
IOUT (A)
20
25
Note:
Parameter guaranteed by design; it is not tested.
14/31
VN5010AK-E Table 11. Truth table
Conditions Normal operation Overtemperature Undervoltage Short circuit to GND (Rsc 10 m) Short circuit to VCC Negative output voltage clamp Input L H L H L H L H H L H L Output L H L L L L L L L H H L
Electrical specifications
Sense (VCSD=0V) (1) 0 Nominal 0 VSENSEH 0 0 0 0 if Tj < TTSD VSENSEH if Tj > TTSD 0 < Nominal 0
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.
Figure 8.
Switching characteristics
VOUT tWon 80% dVOUT/dt(on) tr 10% tf t INPUT td(on) tWoff 90% dVOUT/dt(off)
td(off)
t
Figure 9.
Output voltage drop limitation
Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC
Von Iout Von/Ron(T)
15/31
Electrical specifications Table 12.
ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b (2) ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b (2) III C C C C C C
VN5010AK-E
Electrical transient requirements
Test levels (1) III -75V +37V -100V +75V -6V +65V IV -100V +50V -150V +100V -7V +87V Number of pulses or test times 5000 pulses 5000 pulses 1h 1h 1 pulse 1 pulse Test level results(1) IV C C C C C C Burst cycle/pulse repetition time 0.5 s 0.2 s 90 ms 90 ms 5s 5s 100 ms 100 ms Delays and impedance 2 ms, 10 50 s, 2 0.1 s, 50 0.1 s, 50 100 ms, 0.01 400 ms, 2
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Class C E
Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
16/31
VN5010AK-E Figure 10. Waveforms
Electrical specifications
NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT
UNDERVOLTAGE VUSDhyst VUSD
VCC INPUT CS_DIS LOAD CURRENT SENSE CURRENT
SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT OVERLOAD OPERATION Tj INPUT CS_DIS LOAD CURRENT SENSE CURRENT ILIMH ILIML VSENSEH TR TTSD TRS
current power limitation limitation
thermal cycling SHORTED LOAD NORMAL LOAD
17/31
Electrical specifications
VN5010AK-E
2.3
Electrical characteristics curves
Figure 12. High level input current
Iih (uA)
5 4.5
Figure 11. Off State output current
Iloff (uA)
0.7 0.6
0.5 0.4 0.3 0.2
Off state Vcc= 13V Vin= Vout= 0V
4 3.5 3 2.5 2 1.5 1
Vin= 2.1V
0.1 0 -50 -25 0 25 50 75 100 125 150 175
0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 13. Input clamp voltage
Vicl (V)
7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5 -50 -25 0 25 50 75 100 125 150 175
Figure 14. Input low level
Vil (V)
2
I 1mA in=
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 15. Input high level
Vih (V)
4 3.5 3
Figure 16. Input hysteresis voltage
Vihyst (V)
1 0.9 0.8 0.7
2.5 2 1.5 1
0.6 0.5 0.4 0.3 0.2
0.5 0 -50 -25 0 25 50 75 100 125 150 175
0.1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
18/31
VN5010AK-E Figure 17. On state resistance vs. Tcase
R on (mOhm)
50 45 40 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 150 175
Electrical specifications Figure 18. On state resistance vs. VCC
R on (mOhm)
20 18
I out= 6A Vcc= 13V
16 14 12 10 8 6 4 2 0 0 5 10 15 20 25
Tc= 150C Tc= 125C
Tc= 25C Tc= -40C
30
35
40
Tc (C )
Vcc (V)
Figure 19. Undervoltage shutdown
Vusd (V)
16 14 12
Figure 20. Turn-On voltage slope
dVout/dt(on) (V/ms)
1000 900 800 700
Vcc= 13V RI 2.6Ohm =
10 8 6 4
600 500 400 300 200
2 0 -50 -25 0 25 50 75 100 125 150 175
100 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 21. ILIMH vs. Tcase
Ilimh (A)
80 75
Figure 22. Turn-Off voltage slope
dVout/dt(off) (V/ms)
1000 900
Vcc= 13V
70
800 700
Vcc= 13V RI 2.6Ohm =
65 60 55 50
600 500 400 300 200
45 40 -50 -25 0 25 50 75 100 125 150 175
100 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
19/31
Electrical specifications Figure 23. CS_DIS high level voltage
Vcsdh (V)
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
VN5010AK-E Figure 24. CS_DIS clamp voltage
Vcsdcl (V)
8 7.5
I csd= 1mA
7 6.5 6 5.5 5 4.5 4 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 25. CS_DIS low level voltage
Vcsdl (V)
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
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VN5010AK-E
Application information
3
Application information
Figure 26. Application schematic
+5V
VCC Rprot CS_DIS Dld mC Rprot IINPUT OUTPUT Rprot CURRENT SENSE GND
RSENSE Cext
VGND
RGND
DGND
3.1
3.1.1
GND protection network against reverse battery
Solution 1 : resistor in the ground line (RGND only)
This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. 2. RGND 600mV / (IS(on)max). RGND (- CC) / (-IGND) V
where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/ RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
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Application information
VN5010AK-E
3.1.2
Solution 2 : diode (DGND) in the ground line
A resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift ( 600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor . network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 180k Recommended values: Rprot =10k, CEXT=10nF.
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VN5010AK-E
Application information
3.4
Maximum demagnetization energy (VCC=13.5V)
Figure 27. Maximum turn Off current versus load inductance
100
B
A C
10
I (A) 1 0,1 1 L (mH) 10 100
A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse
VIN, IL Demagnetization Demagnetization Demagnetization
t
Note:
Values are generated with RL=0 . In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C.
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Package and PCB thermal data
VN5010AK-E
4
4.1
Package and PCB thermal data
PowerSSO-24TM thermal data
Figure 28. PowerSSO-24TM PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(C/ W)
55 50 45 40 35 30 0 2 4 6 8 10
PCB Cu heatsink area (cm^ 2)
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VN5010AK-E
Package and PCB thermal data
Figure 30. PowerSSO-24TM thermal impedance junction ambient single pulse
ZTH (C/W) 1000 100 10 1 0,1 0,01 1E-04 0,001
Footprint 2 cm2 8 cm2
0,01
0,1
1
10
100
1000
Time (s)
Equation 1: pulse calculation formula Z =R +Z ( 1 - )
TH
TH
THtp
where = tP/T Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24TM(a)
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/31
Package and PCB thermal data Table 13. Thermal parameters
Footprint 0.08 0.16 6 7.7 9 28 0.002 0.002 0.025 0.75 1 2.2 4 5 9 17 2
VN5010AK-E
Area/island (cm2) R1 (C/W) R2 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
8
8 10
9 17
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VN5010AK-E
Package and packing information
5
5.1
Package and packing information
ECOPACK(R) packages
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 32. PowerSSO-24TM package dimensions
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Package and packing information Table 14. PowerSSO-24TM mechanical data
Millimeters Symbol Min. A A2 a1 b c D E e e3 G G1 H h L N X Y 4.1 6.5 0.55 10.1 2.15 2.15 0 0.33 0.23 10.10 7.4 0.8 8.8 Typ.
VN5010AK-E
Max. 2.47 2.40 0.075 0.51 0.32 10.50 7.6
0.1 0.06 10.5 0.4 0.85 10deg 4.7 7.1
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VN5010AK-E
Package and packing information
5.2
Packing information
Figure 33. PowerSSO-24TM tube shipment (no suffix)
C B
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1)
49 1225 532 3.5 13.8 0.6
All dimensions are in mm.
A
Figure 34. PowerSSO-24TM tape and reel shipment (suffix "TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4
TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 24 4 12 1.55 1.5 11.5 2.85 2
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed Components No components 500mm min
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Revision history
VN5010AK-E
6
Revision history
Table 15.
Date 24-Jan-2006 09-Feb-2007
Document revision history
Revision 1 2 Initial release. Reformatted and restructured. Added Contents, List of tables and List of figures. Added Section 3.4: Maximum demagnetization energy (VCC=13.5V). Document reformatted and restructured. Table 4: Absolute maximum ratings : corrected EMAX value from 506 to 609 mJ. Updated Table 10: Current sense (8V13-Dec-2007
3
12-Feb-2008
4
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VN5010AK-E
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